JCEEES

JCEEES aims to publish original articles covering the theoretical foundations of major computer, electronic and electrical engineering sciences, as well as academic, commercial and educational aspects that propose new ideas for the application and design of artificial intelligence, software and information systems. In addition to wide-ranging regular topics, JCEEES also makes it a principle to include special topics covering specific topics in all areas of interest mainly in computational medicine, artificial intelligence, computer science, and electrical & electronic engineering science.

Index
Original Article
Effect of different transistor technologies on physical design of arithmatic logic unit
Aims: The aim of this open source physical design tool is to observe the impact of miniaturization in transistor technology.
Methods: This study encompasses the utilization of free or open-source software and the design processes involved in both digital and physical design phases within the realm of VLSI design. Additionally, open-source software was utilized as a synthesis tool during the physical design process. This approach allowed us to observe the impact of transistor technology shrinkage not only with licensed software but also with open-source alternatives. One distinguishing feature of this study lies in the verification of the design process through simulations, conducted both after the digital design phase and following the physical design phase. The physical design phase employed the open-source qflow software. Designs for 8-bit, 16-bit, and 32-bit Arithmetic Logic Units (ALUs) were synthesized using transistor technologies of 180nm and 350nm.
Results: The results of the design experiments revealed that reducing the transistor technology scale for designs of the same bit length did not lead to a significant alteration in the number of standard cells comprising the design. However, the number of standard cells increased directly in proportion to the length. As technology continued to shrink, the physical area occupied by the design decreased, while Static Time Analysis (STA) also diminished concurrently with technology scaling.
Conclusion: To promote the proliferation of VLSI design process-es, it is imperative to foster the development and utilization of open-source software. This approach facilitates the expansion of research and education in the field of VLSI design, ultimately augmenting the pool of skilled professionals in this domain


Chupilko, M., Kamkin, A., & Smolov, S. (2021). Survey of open-source flows for digital hardware design. Ivannikov Memorial Workshop (IVMEM), 11-16. doi:10.1109/IVMEM53963.2021.00008
Gaurav, T., Patel, K., & Parekh, R. (2022). RTL to GDSII implementation of RADIX-4 booth multiplier. Int Confer Nanoelectr Nanophot Nanomater Nanobiosci Nanotechnol (5NANO), 1-5. doi:10.1109/5NANO 53044.2022.9828885
Purohit, S., Laddha, P., & Parekh, R. (2021). Implementation and physical design of 8/4-bit signed divider. 8th Int Confer Signal Process Integrat Networks (SPIN), 829-834. doi:10.1109/SPIN52536.2021.9566020
URL-1. (2022). Yosys open synthesis suite. http://www.clifford.at/yosys (date of access: 03-10-2022).
URL-2. (2022). Odin II. https://docs.verilogtorouting.org/en/latest/odin (date of access: 03-10-2022).
URL-3. (2022). Graywolf. https://github.com/rubund/graywolf (date of access: 03-10-2022)
URL-4. (2022). Qrouter. http://opencircuitdesign.com/qrouter (date of access: 03-10-2022)
URL-5. (2022). OpenSTA engine. https://github.com/The-OpenROAD-Project/OpenSTA (date of access: 03-10-2022).
URL-6. (2022). vesta. https://github.com/RTimothyEdwards/qflow/blob/master/src/vesta.c (date of access: 03-10-2022).
URL-7. (2022). vesta. https://github.com/RTimothyEdwards/qflow/blob/master/src/vesta.c (date of access: 03-10-2022).
URL-8. (2022). Netgen 1.5. http://opencircuitdesign.com/netgen (date of access: 03-10-2022).
Kang, S., & Leblebici, Y. (2005). Introduction. In CMOS digital integrated circuits: analysis and design (Tata McGraw Hill ed., Chapter 1, pp. 1-8).
Cao, L. (2021). Multi-objective digital VLSI design optimisation (doctoral dissertation). University of York.
Aydın, M. (2022). Detection of printed circuit board errors with FPGA-based real-time image processing. İstanbul University-Cerrahpaşa.
Bedir, N. (2018). FPGA based 64-bit arithmetic logic unit design. Thesis (PhD), İstanbul University-Cerrahpaşa.
Başak, S. (2011). FPGA based synthesizable processor design. Thesis (PhD), Yıldız Teknik University.
Sırmaçek, B. (2007. Modeling learning algorithm for mobile robot with FPGA. Thesis (PhD), Yıldız Teknik University.
Bakacak, M. (2021). A basic microprocessor design and embedded system implementation for educational purposes. Thesis (PhD), Kırıkkale University.
Ozcan, M. (2023). Different nanometer technologies on ALU (aritmetic logic unit) design. İstanbul University-Cerrahpaşa.
Volume 3, Issue 1, 2025
Page : 1-7
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